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Ultralow Offset Voltage Dual Op Amp AD708
FEATURES
Very high dc precision 30 V maximum offset voltage 0.3 V/C maximum offset voltage drift 0.35 V p-p maximum voltage noise (0.1 Hz to 10 Hz) 5 million V/V minimum open-loop gain 130 dB minimum CMRR 120 dB minimum PSRR Matching characteristics 30 V maximum offset voltage match 0.3 V/C maximum offset voltage drift match 130 dB minimum CMRR match Available in 8-lead narrow body, PDIP, and hermetic CERDIP and CERDIP/883B packages
PIN CONFIGURATION
OUTPUT A -IN A +IN A -VS
1 2 3 4
- +
AD708
A B
- +
8 7 6 5
+VS OUTPUT B -IN B +IN B
05789-001
TOP VIEW (Not to Scale)
Figure 1. PDIP (N) and CERDIP (Q) Packages
GENERAL DESCRIPTION
The AD708 is a high precision, dual monolithic operational amplifier. Each amplifier individually offers excellent dc precision with maximum offset voltage and offset voltage drift of any dual bipolar op amp. The matching specifications are among the best available in any dual op amp. In addition, the AD708 provides 5 V/V minimum open-loop gain and guaranteed maximum input voltage noise of 350 nV p-p (0.1 Hz to 10 Hz). All dc specifications show excellent stability over temperature, with offset voltage drift typically 0.1 V/C and input bias current drift of 25 pA/C maximum. The AD708 is available in four performance grades. The AD708J is rated over the commercial temperature range of 0C to 70C and is available in a narrow body, PDIP. The AD708A and AD708B are rated over the industrial temperature range of -40C to +85C and are available in a CERDIP. The AD708S is rated over the military temperature range of -55C to +125C and is available in a CERDIP military version processed to MIL-STD-883B.
PRODUCT HIGHLIGHTS
1. The combination of outstanding matching and individual specifications make the AD708 ideal for constructing high gain, precision instrumentation amplifiers. The low offset voltage drift and low noise of the AD708 allow the designer to amplify very small signals without sacrificing overall system performance. The AD708 10 V/V typical open-loop gain and 140 dB common-mode rejection make it ideal for precision applications.
2.
3.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
AD708 TABLE OF CONTENTS
Features .............................................................................................. 1 Pin Configuration............................................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Typical Performance Characteristics ............................................. 6 Matching Characteristics............................................................. 9 Theory of Operation ...................................................................... 10 Crosstalk Performance .............................................................. 10 Operation with a Gain of -100................................................. 11 High Precision Programmable Gain Amplifier ..................... 11 Bridge Signal Conditioner......................................................... 12 Precision Absolute Value Circuit ............................................. 12 Selection of Passive Components............................................. 12 Outline Dimensions ....................................................................... 13 Ordering Guide .......................................................................... 13
REVISION HISTORY
1/06--Rev. B to Rev. C Updated Format..................................................................Universal Removed TO-99 Package ..................................................Universal Deleted AD707 References................................................Universal Deleted LT1002 Reference............................................................... 1 Deleted Figure 1................................................................................ 1 Deleted Metalization Photograph .................................................. 5 Moved Figure 25, Figure 26, and Figure 27 to Theory of Operation section .................................................... 10 Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 13 2/91--Rev. A to Rev. B
Rev. C | Page 2 of 16
AD708 SPECIFICATIONS
@ 25C and 15 V dc, unless otherwise noted. Table 1.
Parameter INPUT OFFSET VOLTAGE 2 Drift Long Term Stability INPUT BIAS CURRENT TMIN to TMAX Average Drift OFFSET CURRENT Average Drift MATCHING CHARACTERISTICS 3 Offset Voltage TMIN to TMAX Offset Voltage Drift Input Bias Current TMIN to TMAX Common-Mode Rejection TMIN to TMAX Power Supply Rejection TMIN to TMAX Channel Separation INPUT VOLTAGE NOISE 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz VCM = 13 V TMIN to TMAX VO = 10 V RLOAD 2 k TMIN to TMAX VS = 3 V to 18 V TMIN to TMAX 120 110 110 110 135 140 VCM = 0 V TMIN to TMAX Conditions TMIN to TMAX AD708J/AD708A Min 1 Typ Max1 30 100 50 150 0.3 1.0 0.3 1.0 2.5 2.0 4.0 15 40 0.5 2.0 2.0 4.0 2 60 80 150 1.0 4.0 5.0 130 130 120 120 140 0.6 18 13.0 11.0 35 0.9 0.27 0.18 130 130 5 5 120 120 0.5 0.15 140 Min1 AD708B Typ Max1 5 50 15 65 0.1 0.4 0.3 0.5 1.0 1.0 2.0 10 25 0.1 1.0 0.2 1.5 1 25 50 75 0.4 1.0 2.0 130 130 120 120 140 0.6 12 11.0 11.0 35 0.8 0.23 0.17 130 130 4 4 120 120 0.5 0.15 140 Min1 AD708S Typ Max1 5 30 15 50 0.1 0.3 0.3 0.5 1 1.0 4 10 30 0.1 1 0.2 1.5 1 25 30 50 0.3 1.0 2.0 Unit V V V/C V/month nA nA pA/C nA nA pA/C V V V/C nA nA dB dB dB dB dB V p-p nV/Hz nV/Hz nV/Hz pA p-p pA/Hz pA/Hz pA/Hz dB dB V/V V/V dB dB MHz V/s M G
INPUT CURRENT NOISE
COMMON-MODE REJECTION RATIO OPEN-LOOP GAIN
120 120 3 3 110 110 0.5 0.15
0.23 10.3 10.0 9.6 14 0.32 0.14 0.12 140 140 10 10 130 130 0.9 0.3 60 200
0.23 10.3 10.0 9.6 14 0.32 0.14 0.12 140 140 10 10 130 130 0.9 0.3 200 400
0.23 10.3 10.0 9.6 14 0.32 0.14 0.12 140 140 10 7 130 130 0.9 0.3 200 400
0.35 12 11 11 35 0.8 0.23 0.17
POWER SUPPLY REJECTION RATIO FREQUENCY RESPONSE Closed-Loop Bandwidth Slew Rate INPUT RESISTANCE Differential Common Mode
Rev. C | Page 3 of 16
AD708
Parameter OUTPUT VOLTAGE Conditions RLOAD 10 k RLOAD 2 k RLOAD 1 k TMIN to TMAX AD708J/AD708A Min 1 Typ Max1 13.5 14 12.5 13.0 12.0 12.5 12.0 13.0 60 4.5 135 12 3 5.5 165 18 18 Min1 13.5 12.5 12.0 12.0 AD708B Typ Max1 14.0 13.0 12.5 13.0 60 4.5 135 12 3 5.5 165 18 18 Min1 13.5 12.5 12.0 12.0 AD708S Typ Max1 14 13 12.5 13 60 4.5 135 12 3 5.5 165 18 18 Unit V V V V mA mW mW V
OPEN-LOOP OUTPUT RESISTANCE POWER SUPPLY Quiescent Current Power Consumption Operating Range
1
VS = 15 V VS = 3 V
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. 2 Input offset voltage specifications are guaranteed after five minutes of operation at TA = 25C. 3 Matching is defined as the difference between parameters of the two amplifiers.
Rev. C | Page 4 of 16
AD708 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage Internal Power Dissipation 1 Input Voltage 2 Output Short-Circuit Duration Differential Input Voltage Storage Temperature Range (Q) Storage Temperature Range (N) Lead Temperature (Soldering 60 sec)
1
Rating 22 V VS Indefinite +VS and -VS -65C to +150C -65C to +125C 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics 8-lead PDIP: JC = 33C/W, JA = 100C/W 8-lead CERDIP: JC = 30C/W, JA = 110C/W 2 For supply voltages less than 22 V, the absolute maximum input voltage is equal to the supply voltage.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. C | Page 5 of 16
AD708 TYPICAL PERFORMANCE CHARACTERISTICS
VS = 15 V and TA = 25C, unless otherwise noted.
+VS
COMMON-MODE VOLTAGE LIMIT (V) (REFERRED TO SUPPLY VOLTAGES)
8 7 +V 6 5 4 3 2
05789-005
-0.5 -1.0 -1.5
1.5 1.0 -V
05789-002
SUPPLY CURRENT (mA)
0.5 -VS
1 0
0
5
10
15
20
25
0
3
6
9
12
15
18
21
24
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 2. Input Common-Mode Range vs. Supply Voltage
+VS
OUTPUT VOLTAGE SWING (V) (REFERRED TO SUPPLY VOLTAGES)
Figure 5. Supply Current vs. Supply Voltage
100 90 256 UNITS TESTED -55C TO +125C
-0.5 -1.0 -1.5
+VOUT
80
NUMBER OF UNITS
05789-003
70 60 50 40 30 20 10 0 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3
05789-006
RL = 10k RL = 2k 1.5 1.0 0.5 -VS -VOUT
0
5
10
15
20
25
0.4
SUPPLY VOLTAGE (V)
OFFSET VOLTAGE DRIFT (V/C)
Figure 3. Output Voltage Swing vs. Supply Voltage
35 30 100
Figure 6. Typical Distribution of Offset Voltage Drift
IO = 1mA 10
OUTPUT IMPEDANCE ()
OUTPUT VOLTAGE (V p-p)
25 20 15V SUPPLIES 15 10 5 0 10
AV = +1000 1 AV = +1 0.1
0.01
0.001
05789-004
05789-007
100
1k
10k
0.0001 0.1
1
10
100 FREQUENCY (Hz)
1k
10k
100k
LOAD RESISTANCE ()
Figure 4. Output Voltage Swing vs. Load Resistance
Figure 7. Output Impedance vs. Frequency
Rev. C | Page 6 of 16
AD708
40
INVERTING OR NONINVERTING INPUT BIAS CURRENT (mA)
16 14
OPEN-LOOP GAIN (V/V)
35 30 25 20 15 10
05789-008
12 10 8 VOUT = 10V 6 4 2 0 -60
0
0
1
10
100
-40
-20
0
20
40
60
80
100
120
140
DIFFERENTIAL VOLTAGE (V)
TEMPERATURE (C)
Figure 8. Input Bias Current vs. Differential Input Voltage
Figure 11. Open-Loop Gain vs. Temperature
45 40
INPUT VOLTAGE NOISE (nV/ Hz)
16 14
OPEN-LOOP GAIN (V/V)
35 30 25 20 15 10
05789-009
12 RLOAD = 2k 10 8 6 4
05789-012
1/F CORNER 0.7Hz
5 0
2 0
0.1
1 FREQUENCY (Hz)
10
100
0
5
10
15
20
25
SUPPLY VOLTAGE (V)
Figure 9. Input Noise Spectral Density
140 1s 120
VOLTAGE NOISE (100nV/DIV)
Figure 12. Open-Loop Gain vs. Supply Voltage
0 30 60 90 PHASE MARGIN = 43 120 150 GAIN 180
05789-013
RL = 2k CL = 1000pF
OPEN-LOOP GAIN (dB)
100 80 60 40 20 0 -20
05789-010
TIME (1s/DIV)
0.01
0.1
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 10. 0.1 Hz to 10 Hz Voltage Noise
Figure 13. Open-Loop Gain and Phase vs. Frequency
Rev. C | Page 7 of 16
PHASE (Degrees)
05789-011
5
RL = 10k RL = 2k
AD708
160
2mV/DIV
140
COMMON-MODE REJECTION (dB)
120 100 80 60 40
CH1
05789-014 05789-017
20 0 0.1
1
10
100
1k
10k
100k
1M
TIME (2s/DIV)
FREQUENCY (Hz)
Figure 14. Common-Mode Rejection vs. Frequency
35 FMAX = 2.8kHz 30
OUTPUT VOLTAGE (V p-p)
Figure 17. Small Signal Transient Response; AV = +1, RL = 2 k, CL = 50 pF
2mV/DIV
RL = 2k 25C VS = 15V
25 20 15 10 5 0 1k
CH1
05789-015 05789-018
10k
100k
1M
TIME (2s/DIV)
FREQUENCY (Hz)
Figure 15. Large Signal Frequency Response
160 140
POWER SUPPLY REJECTION (dB)
Figure 18. Small Signal Transient Response; AV = +1, RL = 2 k, CL = 1000 pF
120 100 80 60 40
05789-016
20 0 0.001
0.01
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 16. Power Supply Rejection vs. Frequency
Rev. C | Page 8 of 16
AD708
MATCHING CHARACTERISTICS
32 25C 28 14 16
PERCENTAGE OF UNITS (%)
PERCENTAGE OF UNITS (%)
05789-019
24 20 16 12 8 4 0 -50
12 10 8 6 4
05789-022
2 0 -1.0
-40
-30
-20
-10
0
10
20
30
40
50
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
OFFSET VOLTAGE MATCH (V)
OFFSET CURRENT MATCH (nA)
Figure 19. Typical Distribution of Offset Voltage Match
32 -55C TO +125C 28
Figure 22. Typical Distribution of Input Offset Current Match
160 140 120
PERCENTAGE OF UNITS (%)
24 20 16 12 8
05789-020
PSRR MATCH (dB)
100 80 60 40
05789-023
4 0 -0.5
20 0 -60
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-40
-20
0
20
40
60
80
100
120
140
OFFSET DRIFT MATCH (V/C)
TEMPERATURE (C)
Figure 20. Typical Distribution of Offset Voltage Drift Match
16 14 160 140 120
Figure 23. PSRR Match vs. Temperature
PERCENTAGE OF UNITS (%)
12 10 8 6 4
05789-021
CMRR MATCH (dB)
100 80 60 40
05789-024
2 0 -1.0
20 0 -60
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-40
-20
0
20
40
60
80
100
120
140
INPUT BIAS CURRENT MATCH (nA)
TEMPERATURE (C)
Figure 21. Typical Distribution of Input Bias Current Match
Figure 24. CMRR Match vs. Temperature
Rev. C | Page 9 of 16
AD708 THEORY OF OPERATION
CROSSTALK PERFORMANCE
The AD708 exhibits very low crosstalk as shown in Figure 25, Figure 26, and Figure 27. Figure 25 shows the offset voltage induced on Side B of the AD708 when Side A output is moving slowly (0.2 Hz) from -10 V to +10 V under no load. This is the least stressful situation to the part because the overall power in the chip does not change. Only the location of the power in the output device changes. Figure 26 shows the input offset voltage change to Side B when Side A is driving a 2 k load. Here the power changes in the chip with the maximum power change occurring at 7.5 V. Figure 27 shows crosstalk under the most severe conditions. Side A is connected as a follower with 0 V input, and is forced to sink and source 5 mA of output current. Power = (30 V)(5 mA) = 150 mW Even this large change in power causes only an 8 V (linear) change in the input offset voltage of Side B.
A VIN = 10V 10k VOUTA 2k
B 10 10
VOUTB
2V
VIN = 10V 10k
VOUTA = 2V/DIV
Figure 26. Crosstalk with 2 k Load
B 10 10 A VOUTB IIN = 5mA 2k VIN = 10V
2V
10k
B
VOSB = 1V/DIV
VOUTB
10
10
2V
05789-025
VOUTA = 2V/DIV
Figure 25. Crosstalk with No Load
VOSB = 2V/DIV
INA = 1mA/DIV
Figure 27. Crosstalk Under Forced Source and Sink Conditions
Rev. C | Page 10 of 16
05789-027
05789-026
A
VOUTA
VOSB = 1V/DIV
AD708
OPERATION WITH A GAIN OF -100
To show the outstanding dc precision of the AD708 in a real application, Table 3 shows an error budget calculation for a gain of -100. This configuration is shown in Figure 28. Table 3.
Maximum Error Contribution AV = 100 (S Grade) (Full Scale: VOUT = 10 V, VIN = 100 mV) 30 V/100 mV = 300 ppm (100 k)(1 nA)/10 V 10 V/(5 x 106)/100 mV 0.35 mV/100 mV (0.3 mV/C)/100 mV @ 25C -55C to +125C With Offset Calibrated Out @ 25C -55C to +125C = 34 ppm > 14 bits = 334 ppm > 11 bits = 10 ppm = 20 ppm = 4 ppm = 3 ppm/C = 334 ppm > 11 bits = 634 ppm > 10 bits
VINB -VS +VS S8 S7 S6 S5 OUT 5-8 10k 10k 10k RB 9.9k VINA
AD708
1/2
A0 A1
OUT 1-4
10k S1 S2 S3 S4
10k
10k
9.9k 10k
RA
26.1
26.1
AD7502
100
26.1
1k
10k
10k
AD707
Error Sources VOS IOS Gain (2 k Load) Noise VOS Drift Total Unadjusted Error
AD708
1/2
Figure 29. Precision PGA
The gains of the circuit are controlled by the select lines, A0 and A1, of the AD7502 multiplexer, and are 1, 10, 100, and 1000 in this design. The input stage attains very high dc precision due to the 30 V maximum offset voltage match of the AD708S and the 1 nA maximum input bias current match. The accuracy is maintained over temperature because of the ultralow drift performance of the AD708. To achieve 0.1% gain accuracy, along with high common-mode rejection, the circuit should be trimmed.
100k +VS 0.1F VIN 1k
2
-
7
AD708
3
1/2
6
VOUT
+
4
1k -VS
0.1F
05789-028
To maximize common-mode rejection 1. 2. 3. 4. Set the select lines for gain = 1 and ground VINB. Apply a precision dc voltage to VINA and trim RA until VO = -VINA to the required precision. Connect VINB to VINA and apply an input voltage equal to the full-scale common mode expected. Trim RB until VO = 0 V.
B
Figure 28. Gain of -100 Configuration
This error budget assumes no error in the resistor ratio and no error from power supply variation (the 120 dB minimum PSRR of the AD708S makes this a good assumption). The external resistors can cause gain error from mismatch and drift over temperature.
HIGH PRECISION PROGRAMMABLE GAIN AMPLIFIER
The three op amp programmable gain amplifier shown in Figure 29 takes advantage of the outstanding matching characteristics of the AD708 to achieve high dc precision.
To minimize gain errors 1. 2. 3. Select gain = 10 with the control lines and apply a differential input voltage. Adjust the 100 potentiometer to VO = 10 VIN (adjust VIN magnitude as necessary). Repeat Step 1 and Step 2 for gain = 100 and gain = 1000, adjusting the 1 k and 10 k potentiometers, respectively.
The design shown in Figure 29 should allow for 0.1% gain accuracy and 0.1 V/V common-mode rejection when 1% resistors and 5% potentiometers are used.
Rev. C | Page 11 of 16
05789-029
AD708
BRIDGE SIGNAL CONDITIONER
The AD708 can be used in the circuit shown in Figure 30 to produce an accurate and inexpensive dynamic bridge conditioner. The low offset voltage match and low offset voltage drift match of the AD708 combine to achieve circuit performance better than all but the best instrumentation amplifiers. The outstanding specifications of the AD708, such as open-loop gain, input offset currents, and low input bias currents, do not limit circuit accuracy. As configured, the circuit only requires a gain resistor, RG, of suitable accuracy and a stable, accurate voltage reference. The transfer function is VO = VREF [R/(R + R)][RG/R] The only significant errors due to the AD708S are VOS_OUT = (VOS_MATCH)(2RG/R) = 30 mV VOS_OUT (T) = (VOS_DRIFT)(2RG/R) = 0.3 mV/C To achieve high accuracy, Resistor RG should be 0.1% or better with a low drift coefficient.
+15V
AD708 enables this circuit to accurately resolve the input signal. In addition, the tight offset voltage drift match maintains the resolution of the circuit over the full military temperature range. The high dc open-loop gain and exceptional gain linearity allows the circuit to perform well at both large and small signal levels. In this circuit, the only significant dc errors are due to the offset voltage of the two amplifiers, the input offset current match of the amplifiers, and the mismatch of the resistors. Errors associated with the AD708S contribute less than 0.001% error over -55C to +125C. Maximum error at 25C
10 V 30 V + (10 k )(1 nA )
= 40 V/10 V = 4 ppm
Maximum error at +125C or -55C
50 V + (2 nA )(10 k ) 10 V = 7 ppm @ + 125 C
AD580
2.5V VREF R R = 350
RG 175k
Figure 32 shows VOUT vs. VIN for this circuit with a 3 mV input signal at 0.05 Hz. Note that the circuit exhibits very low offset at the zero crossing. This circuit can also produce VOUT = -|VIN| by reversing the polarity of the two diodes.
1mV 1mV
AD708
R R + R VO
1/2
AD708
887 -15V
05789-030
Figure 30. Bridge Signal Conditioning Circuit
10k 10k IN459 1 10k VIN 5k IN4591 3.75k VO = |VIN| 10k
05789-032
VOUT = 1mV/DIV
1/2
AD708
1/2
VIN = 1mV/DIV
Figure 32. Absolute Value Circuit Performance (Input Signal = 0.05 Hz)
05789-031
5k
AD708
NOTE 1LOW LEAKAGE DIODES
1/2
SELECTION OF PASSIVE COMPONENTS
Use high quality passive components to take full advantage of the high precision and low drift characteristics of the AD708. Discrete resistors and resistor networks with temperature coefficients of less than 10 ppm/C are available from Vishay, Caddock, Precision Replacement Parts (PRP), and others.
Figure 31. Precision Absolute Value Circuit
PRECISION ABSOLUTE VALUE CIRCUIT
The AD708 is ideally suited to the precision absolute value circuit shown in Figure 31. The low offset voltage match of the
Rev. C | Page 12 of 16
AD708 OUTLINE DIMENSIONS
0.400 (10.16) 0.365 (9.27) 0.355 (9.02)
8 1 5
0.005 (0.13) MIN
8
0.055 (1.40) MAX
5
4
0.280 (7.11) 0.250 (6.35) 0.240 (6.10)
0.310 (7.87) 0.220 (5.59)
0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.060 (1.52) MAX 0.195 (4.95) 0.130 (3.30) 0.115 (2.92)
1 4
PIN 1 0.100 (2.54) BSC 0.210 (5.33) MAX 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14)
0.100 (2.54) BSC 0.405 (10.29) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING PLANE 15 0 0.015 (0.38) 0.008 (0.20) 0.320 (8.13) 0.290 (7.37)
0.015 (0.38) MIN
0.015 (0.38) GAUGE PLANE SEATING PLANE 0.430 (10.92) MAX
0.014 (0.36) 0.010 (0.25) 0.008 (0.20)
0.005 (0.13) MIN
COMPLIANT TO JEDEC STANDARDS MS-001-BA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 33. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters)
Figure 34. 8-Lead Ceramic Dual In-Line Package [CERDIP] (Q-8) Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model AD708JN AD708JNZ 1 AD708AQ AD708BQ AD708SQ/883B
1
Temperature Range 0C to +70C 0C to +70C -40C to +85C -40C to +85C -55C to +125C
Package Description 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Ceramic Dual In-Line Package [CERDIP] 8-Lead Ceramic Dual In-Line Package [CERDIP] 8-Lead Ceramic Dual In-Line Package [CERDIP]
Package Option N-8 N-8 Q-8 Q-8 Q-8
Z = Pb-free part.
Rev. C | Page 13 of 16
AD708 NOTES
Rev. C | Page 14 of 16
AD708 NOTES
Rev. C | Page 15 of 16
AD708 NOTES
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C05789-0-1/06(C)
Rev. C | Page 16 of 16

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